1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to dynamic semiconductor memory devices.
2. Description of the Background Art
In recent years, semiconductor memory devices have data bus configurations which are effective in reduction of wiring delay to achieve faster operation.
FIG. 25 is a conceptual view showing a hierarchical data bus. This configuration has been introduced by Kiyoo Ito in Ultra LSI Memory, Baihukan, pp. 168-169.
The semiconductor memory device shown in FIG. 25 has memory blocks #0 to #kxe2x88x921 arranged adjacently and having columns selected by a common column decoder and driver. A column selected in each memory block is connected to a respectively associated local data bus.
In FIG. 25, a column selected in memory block #kxe2x88x921 is connected to a local data bus I/O1 which is connected to a main data bus I/O2. Then a main amplifier MA1 amplifies the data which is in turn transmitted to a global data bus I/O3 and further transmitted by a main amplifier MA2 externally.
This configuration is characterized in that by dividing a local data bus the load capacity of a data bus to be driven by a sense amplifier provided in a block can be reduced to accommodate faster operation without increasing the load driving capability of the sense amplifier provided in the block.
A semiconductor memory device is also adapted to replace a defective memory cell existing therein with a spare memory cell to equivalently repair the defective memory cell and thus improve product yield. In a redundant circuit configuration provided with a spare memory cell (spare word and bit lines) for such repair of a defective memory cell, to improve the utilization efficiency of a spare line (a word line or bit line) and that of a spare decoder for selecting the spare line, a flexible redundancy technique has been proposed (see, e.g., Horiguchi et al., xe2x80x9cA Flexible Redundancy Technique for High-Density DRAM""sxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26 NO.1, JANUARY, 1991, pp. 12-17).
FIG. 26 schematically shows the entire configuration of a semiconductor memory device in a conventional, flexible redundancy configuration.
Referring to FIG. 26, the semiconductor memory device includes four memory arrays MA0-MA3. In each of memory arrays MA0-MA3, a spare word line is arranged for repairing a defective memory cell row. Spare word lines SW00 and SW01, SW10 and SW11, SW20 and SW21, and SW30 and SW31 are arranged in memory arrays MA0, MA1, MA2 and MA3, respectively.
Respectively associated with memory arrays MA0-MA3, row decoders X0-X3 are arranged for driving to selected state a normal word line corresponding to an addressed row.
A column decoder Y0 for decoding a column address signal and selecting an addressed column is arranged between memory arrays MA0 and MA1, and a column decoder Y1 is arranged between memory arrays MA2 and MA3.
The semiconductor memory device also includes spare decoders SD0-SD3 for storing a row address having a defective memory cell and holding a word line corresponding to the defective row address (or a defective normal word line) in non-selected state and driving a corresponding spare word line to selected state when the defective row address is addressed, and an OR circuit G0 receiving a signal output from spare decoders SD0 and SD1 and an OR circuit G1 receiving a signal output from spare decoders SD2 and SD3.
A signal output from OR circuits G0 and G1 is supplied commonly to spare word line drive circuits included respectively in row decoders X0 to X3. Spare decoders SD0-SD3 receive common array address signal bits an-2 and an-1 addressing one of memory arrays MA to MA3 and common in-array address signal bits a0 to an-3 addressing a row in a memory array.
When array address signal bits an-2 and an-1 are supplied and a memory array corresponding thereto is addressed, one of row decoders X0-X3 that is associated with the addressed memory array is activated. OR circuits G0 and G1 are associated with the two spare word lines, respectively, provided in each of memory arrays MA0-MA3.
For example, if memory array MA0 has defective normal word lines W0 and W1, memory array MA1 has a defective normal word line W2 and memory array MA2 has a defective normal word line W3, then the address of normal word line W0 is programmed in spare decoder SD0, the address of normal word line W1 is programmed in spare decoder SD2, the address of normal word line W2 is programmed in spare decoder SD3 and the address of normal word line W3 is programmed in spare decoder SD1.
A signal output from OR circuit G0 designates any of spare word lines SW00, SW10, SW20 and SW30, and a signal output from OR circuit G1 selects any of spare word lines SW01, SW11, SW21 and SW31.
When normal word line W0 is designated, a signal output from spare decoder SD0 is driven to selected state and a signal output from OR circuit G0 is activated. In this state, array address signal bits an-2 and an-1 activates row decoder X0 and the remaining row decoders X1-X3 are held inactive.
Thus the word line drive circuit included in row decoder X0 drives spare word line SW00 to selected state in response to the signal output from OR circuit G0, while a decode circuit provided in row decoder X0 and associated with normal word line W0 is held inactive. Thus, defective normal word line W0 is substituted by spare word line SW00.
Similarly, defective normal word lines W1, W2 and W3 are substituted by spare word lines SW01, SW11 and SW20, respectively.
In the flexible redundancy configuration shown in FIG. 26, one spare word line can be activated by any of a plurality of spare decoders. For example, spare word line SW20 can be driven to selected state by spare decoder SD0 or SD1.
Furthermore, one spare decoder can drive any of a plurality of spare word lines to selected state. For example, spare decoder SD0 can drive any of spare word lines SW00, SW10, SW20 and SW30 to selected state.
Thus the correspondence between spare word line and spare decoder is not one to one and this can enhance the utilization efficiency of spare word line and spare decoder.
More specifically, a spare decoder can be shared by memory arrays to eliminate the necessary of providing a spare decoder for each spare word line and thus reduce chip occupied area.
With such a data bus configuration as the hierarchical data bus configuration described above, substituting a defective normal column with a spare column requires considering how a spare column be arranged, since a local data bus is divided within one memory block.
In such an embedded application as incorporating a semiconductor memory device into a semiconductor device as one block, using a multibit data bus to transfer data allows faster operation and the number of data buses is thus increased. When the number of data buses is increased, consideration must be taken of how a spare column be arranged.
In the flexible redundancy configuration described above, a defective row is repaired through substitution using a spare word line arranged in a memory array including the defective row. Thus, each memory array is disadvantageously required to have a spare word line arranged therein and this degrades the utilization efficiency of the spare word line. Substituting a defective normal word line of a memory array with a spare word line of another memory array to improve the utilization efficiency of the spare word line is not taken into consideration at all, since such substitution would entail complicated control of the circuitry associated with the memory arrays and is thus considered to be avoided.
An object of the present invention is to provide a semiconductor memory device with a multibit data bus, having a redundant circuit configuration advantageous in both operating speed and occupied area in substitution of a defective column.
Another object of the present invention is to provide a semiconductor memory device improved in the utilization efficiency of a spare word line in repairing a defective row.
Briefly speaking, the present invention is a semiconductor memory device constructed on a main surface of a semiconductor substrate, including first to nth memory cell blocks, first to nth local data buses, first to mth global data buses, first to mth connection circuits and a connection controlling circuit, wherein n represents a natural number and m represents a natural number smaller than n.
The first to nth memory cell blocks each have memory cells arranged in rows and columns. The first to nth local data buses are provided for the first to nth memory cell blocks, respectively. The first to mth global data buses communicate stored data with the semiconductor memory device. The first to mth connection circuits are provided for the first to mth global data buses, respectively. An ith one of the first to mth connection circuits selectively connects any one of ith to (i+nxe2x88x92m)th local data buses to an ith global data bus in response to an ith control signal. Wherein i represents a natural number of one to m. The connection controlling circuit outputs first to mth control signals to connect respectively the first to mth global data buses to m ones of the first to nth local data buses.
In another aspect of the present invention, a semiconductor memory device includes a memory cell array, an address program circuit, an address comparing circuit and an address addition circuit.
The memory cell array has memory cells arranged in rows and columns. The memory cell array has redundancy, with the number of the memory cells larger than that of memory cells that corresponds to the maximal value of an accessed address input to the semiconductor memory device. In the address program circuit, a defective address corresponding to a defective one of memory cells is set and the address program circuit outputs the defective address. The address comparing circuit compares an accessed address to a defective address and determines which address is larger. In response to an output from the address comparing circuit the address addition circuit adds a predetermined value to an accessed address to output a converted address. According to the converted address the memory cell array communicates stored data to avoid accessing the defective memory cell.
In still another aspect of the present invention, a semiconductor memory device constructed on a main surface of a semiconductor substrate includes first to nth banks, a global data bus, a plurality of local data buses and a cache block, wherein n represents a natural number of no less than two.
The first to nth banks each have memory cells arranged in rows and columns, each operable independently. The global data bus is shared by the first to nth banks. The plurality of local data buses respectively communicate data between the first to nth banks and the global data bus.
The first bank includes a plurality of normal rows, a plurality of spare rows capable of substituting for any defective row in the first to nth banks that includes a defective memory cell, a plurality of normal bit line pairs shared by the plurality of normal rows and the plurality of spare rows, a plurality of sense amplifiers amplifying potential differences respectively caused in the plurality of normal bit line pairs, and a gate circuit selectively connecting one of the plurality of bit line pairs to an associated local data bus. The cache block includes a cache row provided for the first bank and communicating data with the global data bus when two rows of the normal and spare rows of the first bank are accessed simultaneously.
Thus a main advantage of the present invention is that in a configuration having a large number of data buses a column redundancy system can be achieved without changing an order of the data buses and a complex order switching circuit can thus be dispensed with to reduce chip area and also achieve rapid operation.
A another advantage of the present invention is that in a multibank configuration, flexible row redundancy can be achieved and thus redundant repairing ability can be enhanced and chip area can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.